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10th WorldS4 2026 has ended
Thursday July 30, 2026 11:30am - 1:00pm BST

Authors - Ioannis Patias, Koutaro Hachiya
Abstract - The rapid growth of compute-intensive applications has intensified the need for selecting appropriate hardware accelerators. This paper presents a workload-to-architecture framework that explains when GPUs, FPGAs, or ASICs are most suitable, based on four determinants: parallelism granularity, memory behavior, dataflow regularity, and specialization depth. We organize representative workload classes—dense linear algebra, sparse/irregular algorithms, streaming signal processing, bit-level control workloads, and deep learning (training/inference)—and discuss how each class aligns with the execution and memory models of the three accelerator families. Our analysis highlights that GPUs excel in throughput-oriented, data-regular workloads; FPGAs provide deterministic latency via spatial pipelining and customized data paths; and ASICs achieve the best performance-per-watt for stable, high-volume tasks. The resulting framework provides practical guidance for accelerator selection and motivates heterogeneous system design.
Paper Presenters
Thursday July 30, 2026 11:30am - 1:00pm BST
Virtual Room A London, UK

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